The present invention relates to a non-volatile semiconductor memory device, and particularly to a non-volatile semiconductor memory device built in a processor such as a microcomputer. More particularly, the present invention relates to a configuration which performs writing and erasing of a non-volatile semiconductor memory device.
One flash memory corresponding to a non-volatile semiconductor memory device has heretofore been used mainly independently in applications or the like which store a control program and data of a cellular phone. In order to store a control program and data of a microcomputer, however, applications in the form of the flash memory being built in the microcomputer have been widened in recent years.
The microcomputer having built such a flash memory therein needs to realize a memory having required minimum memory capacity in as small an area as possible in terms of a limitation to a chip size. Since the microcomputer having built such a flash memory therein is used in various applications, there is a need to develop a wide variety of microcomputer products in a common platform. Therefore, in order to meet diversified programs, it is desired that division units of a program storage area of the flash memory can be changed flexibly. The change of the division units corresponding to the program size means such a configuration that if descried concretely, erase and write operations are performed in division units of small memory capacity ranging from about 128 bytes to 1K bytes.
A flash memory cell stores therein data according to the amount of electrical charge accumulated in its floating gate. Thus, the flash memory needs to execute erasing on a target memory cell before the writing of data. Upon the erase operation, the difference in potential between each well and a control gate is utilized. Thus, a reduction in erase unit means that a memory cell array area with memory cells arranged therein is divided into a plurality of small areas by wells. In this case, the area increases by well separation, thus resulting in contradiction to small area requirements that need for built-in applications.
One example of a method for increasing the number of erase units without increasing a well's division number has been shown in a patent document 1 (Japanese Unexamined Patent Publication No. Hei 09(1997)-153292). In the configuration shown in the patent document 1, a voltage of the same level as a well potential is applied to word lines arranged with respect to memory cells lying in non-selected rows. In each of the memory cells lying in the non-selected rows, its control gate and well become the same potential, and the transfer of electric charge between its floating gate and well is prohibited. Thus, the erase unit is set to a word line unit.
In the flash memory, a high voltage is applied to the corresponding memory cell upon erasing, so that deterioration of an insulating film located below the floating gate occurs. One example of a configuration for achieving suppression of degradation of each memory cell by such erasing has been shown in a patent document 2 (Japanese Unexamined Patent Publication No. 2000-298992). In the patent document 2, data translation is performed in a flash memory cell that stores multivalued data therein, and an area highest in threshold voltage and an area close to it are used for data storage. Using the limited area of the threshold voltage areas that store the multivalued data therein, the amount of electrical charge that passes through the insulating film lying below the floating gate is reduced and deterioration of the insulating film is suppressed during a data rewriting cycle.
The microcomputer with the flash memory built therein is different from a microcomputer utilizing a conventional mask ROM (Read-Only Memory) as a program memory. A control program can be changed on an on-board at a delivery destination. Speeding-up with respect to erasing and writing of the control program is required.
A configuration for realizing high-speed writing in a flash memory has been shown in a patent document 3 (Japanese Unexamined Patent Publication No. He 06(1994)-124596). In the configuration shown in the patent document 3, a memory cell array is divided into a plurality of sectors. Upon data rewriting, sectors each placed in a non-written state or a sector lowest in the number of erases is extracted and the rewriting of data is executed thereon. Deterioration of memory cell characteristics of each sector due to the concentration of erasing on specific sectors is suppressed. Since data is written into a new sector, easing of the new sector becomes unnecessary upon rewriting, and the writing of data can be executed at high speed.